library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity io_port is
	generic (PortAddress : integer range 0 to 255 := 0);
	port (
		CLK_n   : in std_logic := '1';
		CS		: in std_logic := '0';
		
		RD_n    : in std_logic := '1'; --active low, set data on bus, keep until RD_n goes to '1'
		WR_n    : in std_logic := '1'; --active low, when low, data bus contains valid data, latch in on next clock edge
		DATA_IN : in std_logic_vector(7 downto 0); -- data from CPU, to us
		DATA_OUT: out std_logic_vector(7 downto 0); -- data to CPU, set by us
		PORTS_i : in std_logic_vector(7 downto 0); -- only for address "00000000", input to CPU
		PORTS_o : out std_logic_vector(7 downto 0)
	);
end io_port;

architecture rtl of io_port is
begin
	get_addr: process (CLK_n)
	begin
		if CLK_n'event and CLK_n = '0' then 
			if CS = '1' then
				if  (WR_n = '0' ) then
					PORTS_o <= DATA_IN;
				end if;
			end if;
		end if;
	end process;
	
	DATA_OUT <= PORTS_i;
	
end;